The present invention relates to integrated circuits (ICs), and more particularly to ICs which include at least a deep trench memory cell in which the trench walls have been roughened for enhanced capacitance using polysilicon as a roughening agent.
A memory cell in an IC comprises a transistor and an associated capacitor. The capacitor, which is typically formed in a portion of a trench, consists of a pair of conductive plates, i.e., electrodes, which are separated from each other by a node dielectric material. Information or data is stored in the memory cell in the form of charge accumulated on the capacitor. As the density of the ICs with memory cells is increased, the area for the capacitor becomes smaller and the amount of charge the capacitor is able to accumulate is reduced. Thus, with less charge to detect, reading the information or data from the memory cell becomes much more difficult.
With a limited fixed space or volume for the capacitor of a memory cell in a highly integrated circuit, there are three known techniques for increasing the amount of charge within a fixed space or area. These three known techniques include: (1) decreasing the thickness of the dielectric material, i.e., node dielectric, that is located between the capacitor plates; (2) changing the dielectric material to one with a dielectric constant higher than SiO2 or Si3N4; or (3) increasing the surface area of the space to be used for the capacitor.
Of the above mentioned techniques, solution (3) is the most viable because the other two solutions have drawbacks associated therewith. For example, solution (1), which thins the capacitor dielectric, also increases leakage currents that may affect the memory retention performance of the capacitor and the reliability of the memory cell. Solution (2), which purports to change the dielectric material to a higher-dielectric material, will only cause a slight improvement in charge storage because the dielectric constant of suitable alternative dielectrics is only slightly higher than the dielectric material currently being used. Moreover, the substitution of alternative dielectrics may be more complicated, more expensive and provide fabrication problems that are heretofore unknown. Accordingly, solution (3), i.e., increasing the surface area of the space to be used for the capacitor, provides the most promise for substantially improving the amount of charge stored without causing any of the problems mentioned for solutions (1) and (2) above.
One previous solution to increase the surface area of the capacitor is to replace common stack capacitor technology with trench capacitors. In common stack capacitor technology, the capacitor is built on a surface created on a semiconductor substrate. Whereas in trench capacitor technology, the capacitor is formed within a trench that is formed in a semiconductor substrate itself. An increase in depth of the trench, increases the surface area of the capacitor. However, the depth of the trench is limited by present fabrication methods and tools. This problem is further compounded by the forever increasing density of ICs achieved by dimensional shrinkage. To offset the loss of surface area due to a reduction in width, the depth of the trench must be further increased to the point where the necessary depth is not achievable or becomes prohibitively expensive.
Another prior art method to increase the surface area of the capacitor is to provide capacitor plates that contain textured or roughened surfaces in the deep trench adjacent to the dielectric material. A capacitor plate having roughened surface area increases the amount of surface area of the capacitor due to the peaks and valleys of the roughened surface. With this prior art structure and method, the depth of the trench is maximized and the rough surface of the plates is designed to give maximum surface area based on a cross-section of the roughened surface so that the surface area is three-dimensional at the interface of the plates and the dielectric material. However, this prior art method may result in microscopic roughness with sharp features or peaks on the order of a few Angstroms on the capacitor plate which may give rise to leakage through the dielectric material.
Co-assigned U.S. application Ser. No. 09/559,884, filed Apr. 26, 2000 provides a method of roughening the walls of a deep trench capacitor for increasing the charge storage capability of the trench without current leakage. In that application, oxidizable hemispherical silicon grains (HSG) are employed. When such material is employed in roughening the interior walls of the trench, residual polysilicon may remain on the trench walls therefore allowing current leakage to occur.
In view of the above mentioned drawbacks, there is a need to develop a new and improved method of increasing the surface area of the capacitor in a deep trench memory cell without causing any substantial current leakage.
One object of the present invention is to provide a method of fabricating a deep trench memory cell such as a deep trench dynamic random access memory (DT DRAM) cell in which the surface area of the capacitor has been increased.
A further object of the present invention is to provide a method of fabricating a deep trench memory cell in which the capacitor surface area is increased without causing any substantial current leakage through the cell.
These and other objects and advantages are obtained in the present invention by utilizing a method wherein the increased capacitor surface area of the deep trench memory device is obtained by roughening the interior walls (sidewalls and bottom wall portion) of the trench using polysilicon as a roughening agent. It is noted that the term xe2x80x9cdeep trenchxe2x80x9d is used herein to denote a trench that has a depth of from about 2 to about 12 xcexcm, more particularly, 6-8 xcexcm. It is also noted that the inventive method provides an alternative method to the one disclosed in co-assigned U.S. Application Ser. No. 09/559,884, filed Apr. 24, 2000.
Specifically, the method of the present invention comprises the steps of:
(a) forming a deep trench in a semiconductor substrate, said deep trench having an upper region, a lower region and interior walls;
(b) forming a collar stack in said upper region of said deep trench;
(c) forming a discontinuous polysilicon layer on exposed interior walls of the lower trench region, said discontinuous polysilicon layer having gaps therein which expose portions of said substrate;
(d) oxidizing the lower trench region such that the exposed portions of said substrate provided by the gaps in the discontinuous polysilicon layer are oxidized into oxide material which forms a smooth and wavy layer with said discontinuous polysilicon layer; and
(e) etching said oxide material so as to form smooth hemispherical grooves on the walls of the trench region.
The above mentioned processing steps, which can be used with conventional deep trench processing steps, provide an estimated area enhancement of about 1.5 to about 2 times that of a bare Si surface. Contrary to the case of HSG, no residual polysilicon remains on the interior walls of the trench after etching; therefore, no current leakage due to polysilicon grain boundaries is observed when the present invention is employed.
In one embodiment of the present invention, the lower region of the deep trench is subjected to an isotropic etching process prior to depositing the discontinuous polysilicon layer on the trench walls. When this embodiment is employed, the lower trench region is broadened to extend beyond that of the upper trench region.
In addition to the above-mentioned method, the present invention also provides an alternative method which can be used to increase the surface area of a capacitor in a deep trench memory cell. Specifically, the alternative method comprises the steps of:
(a) forming a deep trench in a semiconductor substrate, said deep trench having an upper region, a lower region and interior walls;
(b) forming a SiO2 layer on exposed interior walls of said deep trench in said lower region;
(c) forming a discontinuous polysilicon layer on said SiO2 layer provided in step (b), said discontinuous polysilicon layer having gaps therein which expose portions of said SiO2 layer;
(d) etching any exposed SiO2 layer not covered by said discontinuous polysilicon layer so as to expose portions of said semiconductor substrate;
(e) laterally etching said exposed portions of said semiconductor substrate so as to form a recessed pocket in said deep trench, while simultaneously etching said discontinuous polysilicon layer so as to expose remaining portions of said SiO2 layer; and
(f) etching said remaining portions of said SiO2 layer.
As in the previous method, a collar oxide may be formed in the upper region of the deep trench prior to conducting step (b) of the alternative method.